Distributed logic simulation: time-first evaluation vs. event driven algorithms

With the increasing complexity of VLSI circuits, simulation of digital circuits is becoming a more complex and time-consuming task. General purpose parallel processing machines are increasingly being used to speed up a variety of VLSI CAD applications. All previous works on mapping sequential logic simulation algorithms onto general purpose parallel machines were centered around using Event-Driven algorithm, and do not satasfactorily address the suitability of a particular sequential algorithm for parallel implementation. In this paper, we present analysis of two distributed simulation algorithms: the centralized-time Event-Driven algorithm and the Time-First evaluation algorithm, mapped onto a network of workstations. We present results over a wide range of ISCAS85 and ISCAS89 benchmark circuits, to show that the Time-First evaluation algorithm is likely to be a viable alternative to the event-driven algorithm in the domain of parallel logic simulation